Phase-locked loops (PLLs) are often used within digital circuits to generate an output clock signal responsive to an input clock. A digital integrated circuit such as a programmable logic device may have several PLLs generating a plurality of clock signals.
Because the operation of a digital integrated circuit occurs synchronously to the transition of its various clock signals, the accuracy of each clock signal is important for reliable operation. Ideally, each clock signal would have its edge transitions occur precisely when intended by a circuit designer. The drift of a clock signal from its intended transitions is deemed as jitter. As a clock jitters too much, various errors or glitches occur in circuit operation.
The measurement of jitter has been much studied and characterized because control of jitter is so important for proper circuit operation. In that regard, there are various types of jitter measurement such as cycle-to-cycle jitter and period jitter. In particular, a static phase offset jitter measurement has been defined between the input clock and feedback input clock for a PLL. Turning now to FIG. 1, the time relationship between a differential PLL input clock signal (CK) and a corresponding jittered differential feedback input clock (FBIN) is illustrated. As defined in the Joint Electron Device Engineering Council (JEDEC) standard JESD82-11, the skew between the edge transitions of CK and FBIN at the nth clock cycle [defined as t(φ)n] is averaged over a relatively large number of samples (clock cycles) to generate the static phase offset value t(φ) according to the following expression:t(φ)=Σ1n=N t(φ)n/N where N is a sufficiently large number of samples. The JEDEC standard specifies 2000 samples.
Another important jitter measurement relates to the ability of a PLL or other type of frequency synthesizer to respond to a modulated input clock. For example, to reduce the electromagnetic interference (EMI) generated by a PLL, the input clock may be spread-spectrum modulated. Turning now to FIG. 2, a typical spread spectrum modulation (SSC1) frequency profile for a PLL input clock 200 is illustrated. As this input clock changes frequency, a corresponding PLL must be able to keep its output clock within acceptable jitter limits for proper operation of a digital circuit using the PLL's output clock. The JEDEC standard JESD82-11 defines a parameter known as the dynamic phase offset (DPO) that is commonly used to quantify the spread spectrum compliance of a PLL. However, unlike other well-known jitter parameters such as phase offset, the JEDEC standards set forth no definition or standard of how to measure DPO. Despite the ill-defined nature of DPO, manufacturers advertise the DPO performance of their circuits. However, because there is no standardized and accepted DPO test measurement method, a user cannot be sure of the test conditions used by a given manufacturer to establish their DPO performance.
Accordingly, there is need in the art for a test method and corresponding apparatus to properly measure the DPO performance of circuits such as PLLs or frequency synthesizers.